Intel Xeon Phi Training Workshop

Intel Xeon Phi Training Workshop Flyer

Dates:  Monday & Tuesday, September 14 & 15, 2015


Register for a two-day Intel Xeon Phi Training Workshop scheduled for Monday & Tuesday, September 14 & 15, 2015 at the University of Hawaiʻi (UH) Mānoa campus.

The UH’s Information Technology Services (ITS) Cyberinfrastructure (CI) will host the Intel Xeon Phi Training Workshop at the Information Technology Center. The workshop is free and open to all Hawaiʻi-based institutions.  Funds are available for traveling and hotel accommodation from the neighboring islands.

The Intel Xeon Phi Training Workshop is a collaboration with the UH’s ITS CI, Clemson University Cyberinfrastructure Technology Integration (CITI) Group and the Texas Advanced Computing Center (TACC) at the University of Texas. Funding is made possible by the National Science Foundation.

This workshop is an introduction to the Xeon Phi for programmers and non-programmers alike. It includes an overview of the device and the three primary programming/execution models that target the Many Integrated Core (MIC) architecture. In addition to instructor demonstrations, the workshop includes two hands-on lab sessions: a basic lab that amounts to a tour of the Xeon Phi, and a more advanced session during which participants can explore the programming model(s) that interest them.

Workshop will cover basic architecture of Intel Xeon Phi and Stampede cluster. Introduction to using Intel Xeon Phi will be divided into sections for both novice and advanced programmers starting from basic usage and automatic offload to native, symmetric and offload execution models.

Second day of the workshop will be devoted to exploring best practices for porting existing code to Intel Xeon Phis. We will continue with two lecture sessions and advanced lab. Participants are welcome to spend this time with the tutors discussing options for porting their own codes.

For more information regarding agenda, tutors and registration, go to